(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to improve the adhesion of a molding compound, applied after a gold wire bond procedure, to the top surface of an underlying semiconductor chip.
(2) Description of Prior Art
The use of damascene processing to obtain metal interconnect structures, has allowed more devices to be placed on a semiconductor chip, when compared to counterpart semiconductor chips, comprised using conventional patterning procedures, such as photolithography and dry etching, to form the desired metal interconnect structures. The damascene metal interconnect structure, formed in a damascene opening, in an insulator layer, via chemical mechanical polishing procedures, exhibits a smooth, top surface topography, comprised of the top surface of the damascene metal structure, and the top surface of the insulator layer, in which the damascene pattern was formed in. The smooth top surface topography is. a result of the chemical mechanical polishing procedure, performed after a metal deposition, and used to remove the region of unwanted metal, from the top surface of an insulator layer, leaving the damascene metal structure only in the damascene opening. For most wiring levels the smooth topography is an advantageous feature, allowing subsequent overlying wiring levels, to be easily formed, without complications from an underlying wiring level, exhibiting a severe topography. The smooth top surface topography, can however present difficulties, when introduced as the final, or top level, of the semiconductor chip, prior to a wire bonding procedure, and prior to applying a protective molding compound on the completed semiconductor chip. After forming wire bonds, such as gold wire bonds, to a damascene metal structure, a molding compound is applied to protect the completed semiconductor chip from subsequent mechanical operations, encountered during assembly and packaging procedures. However the smooth top surface topography presented by the damascene type metal structures, and by overlying passivation layers, degrade the adhesion between the protective molding compound, and the underlying semiconductor chip, comprised with the smooth top surface topography.
This invention will describe methods in which the adhesion of a molding compound, applied to an underlying semiconductor chip, is improved via procedures used to add topography to a top surface comprised with damascene metal structures. A first procedure will describe a method for recessing the metal damascene structure, in the damascene opening, thus increasing the severity of the top surface topography, while a second procedure will teach a method of recessing the insulator layer, surrounding the metal damascene structure, again resulting in the desired increase for the top surface topography. The non-smooth, top surface topography, allows improved adhesion between a subsequent, overlying molding compound, and the underlying semiconductor chip, to be realized. Prior art, such as Kim et al, in U.S. Pat. No. 5,804,883, and Eskidlsen et al, in U.S. Pat. No. 5,336,456, describe procedures to reduce stress, and to reduce fracture, of molding compounds, however these prior arts do not describe the procedures used to create the non-smooth, top surface topography, needed to improve the adhesion of the molding compound, to underlying surfaces.